The present invention relates generally to digital signal processing, and specifically to digital receivers for AC-coupled lines.
Local-area networks (LANs) or communication devices transmitting and receiving digital signals commonly operate on standards such as Ethernet 10BASE-T or 100BASE-TX. The 100BASE-TX Ethernet standard enables communication at 100 Mb/s on unshielded twisted pair (UTP) copper wire by using MLT-3 encoding. MLT-3 encoding transmits xe2x80x9c1xe2x80x9ds as ordered level changes between 3 levels {1, 0, xe2x88x921}, whereas xe2x80x9c0xe2x80x9ds are transmitted as the same level as the previous symbol. Thus the signal 1111111 could be encoded as {0, 1, 0, xe2x88x921, 0, 1, 0, xe2x88x921}, and the signal 1111011100 could be encoded as {0, 1, 0, xe2x88x921, xe2x88x921, 0, 1, 0, 0, 0}. In principle, other forms of ordered level change encoding can also be used. For example, instead of 3 ordered level changes, signals could also be encoded with 5 ordered level changes {2, 1, 0, xe2x88x921, xe2x88x922}.
One of the advantages of ordered level change encoding is that the high frequency components of the signal are reduced. For MLT-3 encoding with signals clocked at a standard rate of 125 MHz (8 ns per symbol), the signal frequency varies from 0, for a run of xe2x80x9c0xe2x80x9ds, to a maximum of 31.25 MHz (125/4) for a run of xe2x80x9c1xe2x80x9ds. (125 MHz is a nominal frequency, and in practice the frequency will vary slightly from the nominal.) The relatively low signal frequency is advantageous in reducing electromagnetic interference (EMI) and relaxing frequency-related demands on signal processing equipment and wiring. However, MLT-3 encoding creates inherent problems for receivers, particularly when the receivers are at the end of long runs (of the order of 100 m) of cable, as described hereinbelow.
MLT-3 signals are transmitted and received via transformers, so that there is no path for DC between transmitter and receiver. If a continuous string of xe2x80x9c0xe2x80x9ds is transmitted, then there may be an effective DC level in the transmitted signal, which needs to be detected by the receiver. At the receiver, the signal is detected by digitizing and comparing the received signal to the receiver""s baseline. In order to correctly detect DC levels, the receiver""s baseline must be constantly adjusted for baseline wander (BLW)xe2x80x94since BLW or the inaccurate correction thereof causes errors in the recovered signal.
The incoming signal is sampled and digitized by an A/D converter, preferably operating at the minimum theoretical sample rate for the A/D converter, equal to the clock rate of the signal, i.e., the nominal 125 MHz. In order for the A/D converter to operate efficiently, the receiver has to recover the exact clock timing, both in frequency and in phase, from the received signal.
In a paper by Mueller and Muller, xe2x80x9cTiming recovery in digital synchronous data receivers,xe2x80x9d IEEE Transactions on Communications, pp 516-531, Vol. 24, May 1976, which is herein incorporated by reference, the authors propose a timing recovery algorithm. The paper is accepted in the art as the basis for timing recovery algorithms, and relies on selecting a timing function that is zero at an assumed best sampling point. The phase of the sampling point is then adjusted until its phase is zero.
In a paper by Fertner and Solve, xe2x80x9cSymbol-rate timing recovery comprising the optimum signal-to-noise ratio in a digital subscriber loop,xe2x80x9d IEEE Transactions on Communications, pp 925-936, Vol. 45, August 1997, which is herein incorporated by reference, the authors investigate a recovery algorithm that is based on the correlation between a mean-square error from a decision feedback equalizer and an arriving sample signal. The authors also point out practical complications involved in the relatively conceptually straightforward derivation of Mueller and Muller.
FIG. 1 is a graph showing the typical received shape of an 8 ns positive pulse after transmission along different lengths of unshielded twisted pair category 5 (UTP cat-5) cables. The pulse, comprising a sharp leading edge and a less sharp trailing edge, drops in height exponentially, and increases in width with increasing cable length. Consequently, for cable lengths over 100 m, it becomes increasingly difficult to recover the clock and distinguish one pulse from the next.
FIG. 2 shows a composite received signal 11 for a cable 130 m long, given an input signal 13 of 1, 1, 1, 1, 0, xe2x88x921, 0, 1, wherein 1 corresponds to a positive pulse and xe2x88x921 corresponds to a negative pulse. The circles on composite graph 11 correspond to measured signals spaced 8 ns apart. This graph illustrates the difficulty of recovering the clock and the input signal values, since the measured values are not simply related to the input signal of 1, 1, 1, 1, 0, xe2x88x921, 0, 1.
FIG. 3 is a block diagram of a receiver 20 used to detect 100BASE-TX signals of the type shown in FIG. 2, as is at present known in the art. Signals from a magnetics (transformer) stage are input to an automatic gain control (AGC) amplifier 14, and transferred to an analog summer 18, wherein a BLW correction is added. The result is transferred to an A/D converter 21. The A/D converter generates corresponding digital signals, sampled according to an input clock signal from a PLL 40 and phase multiplexer 42, and the digitized signals are transferred to a digital signal processing (DSP) core 48. The clock signal is synchronized in frequency and phase with the incoming input signal, in order to minimize conversion errors in the A/D converter.
DSP core 48 comprises a forward equalization (FEQ) module 26, an adder 28, a decision (DEC) module 30, and a decision feedback equalizer (DFE) module 32, which together act to supply data to a baseline wander correction module 24. BLW correction module 24 supplies the aforementioned (analog) BLW correction signal to summer 18. Typically, the magnetics stage has a non-linear inductance, and acts as a high pass filter, and BLW module 24 comprises a matching low pass filter whose frequency response is adjustable. The characteristics of the low pass filter are pre-adjusted to minimize BLW. The high pass filter characteristics of the magnetics stage, however, depend on the DC current flowing in the magnetics stage, so that the characteristics are not fixed and are difficult to predict.
DSP core 48 also comprises a DSP control 36 and a timing control 38. On the basis of signals output by decision module 30, DSP control 36 supplies data to timing control 38. Timing control 38 controls the frequency and phase of the clock signal supplied by multiplexer 42, for example, according to the aforementioned method of Mueller and Muller. Core 48 transfers the equalized, BLW-corrected signals in MLT-3 format to module 46, wherein the signals are processed further for transmission in binary format, preferably in a non-return-to-zero (NRZ) format.
Other existing receivers use analog equalizers, such as high pass filters; these equalizers inherently enhance the noise at the same time as they enhance the high-frequency gain. Errors in the assumed parameter values of the equalizers lead to an error in reconstructing the BLW. Furthermore, any decision error leads to symbol error and inaccurate BLW correction for a relatively long time period.
In order to overcome the inherent limitations of poor transmission of low frequency signals through the input transformers, existing receivers use complicated adaptive algorithms to reconstruct the transmitted DC level. Existing receivers continuously monitor the signal baseline to correct BLW.
It is an object of the present invention to provide an improved receiver for high frequency digital signals.
It is a further object of some aspects of the present invention to provide methods and devices for substantially eliminating the effects of baseline wander in a receiver.
It is a further object of some aspects of the present invention to provide improved methods and devices for synchronizing a receiver clock with an input signal clock rate.
It is a yet further object of some aspects of the present invention to provide improved methods and devices for equalizing received signals.
In preferred embodiments of the present invention, a receiver comprises an A/D converter with a variable reference, a pre-decoding section, a digital equalization section, and an output section. The A/D converter preferably accepts 100BASE-T signals, and the output section preferably outputs the signals in NRZ format. Signals input to the receiver are transferred directly to the A/D converter, with substantially no intervening signal adjustment for baseline wander, unlike receivers at present known in the art. The necessity for additional compensation for baseline wander is substantially eliminated by the pre-decoding section, wherein each signal sampled and digitized by the A/D converter is subtracted from a preceding sample, thus substantially eliminating the effects of baseline wander (BLW).
In preferred embodiments of the present invention, the A/D converter is placed before the pre-decoding section. Alternatively, the pre-decoding section is placed-before the A/D converter.
In some preferred embodiments of the present invention, the equalization section has a unique pipeline architecture, enabling it to operate at substantially faster clock rates, and with substantially fewer components, compared to equalizers known in the art. The equalization section comprises both forward equalization and decision feedback equalization stages on a common pipeline, with multiplicative coefficients determined using an adaptive process, preferably a least mean squares adaptation. Preferably, clock recovery from the incoming signal is performed by measuring differences between two or more of the coefficients evaluated in the equalization section, using the differences to give substantially better clock recovery for weaker signals than methods at present known in the art. Most preferably, differences are measured between one coefficient in the decision feedback equalization stage, and one coefficient in the forward equalization stage.
There is therefore provided, in accordance with a preferred embodiment of the present invention, a receiver of baseband signals from a communications line characterized by baseline wander, including:
a pre-decoding section, which receives and samples the signals and subtracts each sample from a preceding sample so as to generate corrected data; and
an equalization section, which receives the corrected data and generates equalized output data representative of data input to the line and generally free of the baseline wander.
Preferably, the receiver includes an A/D converter which digitizes the signals and transmits the digitized signals to the pre-decoding section. Alternatively, the A/D converter digitizes the corrected data and transmits the digitized corrected data to the equalization section.
Preferably, the equalization section includes a pipeline, including one or more delay stages and one or more respective adders, and the pre-decoding section includes an input to the pipeline.
Preferably, the baseband signals are encoded in an ordered level change format, most preferably an MLT-3 format.
Preferably, the equalization section includes a decision module which compares the equalized data to one or more predetermined thresholds and responsive thereto outputs decision data corresponding to a level of the input data. In a preferred embodiment, the decision module outputs an error signal, indicative of a deviation of the equalized output data relative to the level of the input data, which error signal is fed back to an input of the equalization section. Preferably, the equalization section generates, responsive to the error signal, one or more forward equalization coefficients, which multiply the corrected data, and one or more decision feedback equalization coefficients, which multiply the decision data, and the multiplied corrected data and decision data are summed to generate the equalized data. Further preferably, the receiver includes a clock generator, which provides a timing signal to control the sampling of the A/D converter, wherein the generator adjusts the timing signal responsive to one or more of the coefficients.
There is also provided, in accordance with a preferred embodiment of the present invention, a receiver of baseband signals from a communications line, including:
an A/D converter, which samples and digitizes the signals to generate digitized data;
an equalization section, which receives the digitized data and generates equalized output data representative of data input to the line;
a-decision module, which compares the equalized data to one or more predetermined thresholds and responsive thereto outputs decision data indicative of a level of the data input to the line; and
a clock generator which generates a variable clock signal responsive to the decision data, which clock signal is used to time the sampling of the A/D converter.
Preferably, a phase of the clock generator is varied responsive to the decision data. Most preferably, the clock generator provides a plurality of clock signals having different, respective phases, such that the phase of the clock generator is varied by selecting one of the plurality of signals responsive to the decision data.
Additionally or alternatively, a frequency of the clock generator is varied responsive to the decision data.
Preferably, the clock signal is generated responsive to an error signal indicative of a deviation of the equalized output data relative to the data input to the line.
In a preferred embodiment, the equalization section includes a processing pipeline, which generates, responsive to the error signal, one or more equalization coefficients, including one or more forward equalization coefficients which multiply the digitized data, and one or more decision feedback equalization coefficients, which multiply the decision data, and the clock signal is generated responsive to one or more of the coefficients. Most preferably, the clock generator generates the clock signal responsive to a precursor coefficient of the one or more forward equalization coefficients and a most significant one of the one or more decision feedback equalization coefficients.
Further preferably, the clock generator generates the clock signal responsive to an integration of the at least one of the coefficients over a predetermined number of clock cycles, wherein the clock signal is varied responsive to a primary difference between the integration and the at least one of the coefficients. Alternatively or additionally, the clock signal is varied responsive to a secondary difference corresponding to a variation over time in the primary difference.
In a preferred embodiment, the clock generator generates the clock signal responsive to a difference between one of the forward equalization coefficients and one of the decision feedback equalization coefficients. Preferably, the clock generator generates a frequency offset of the clock signal responsive to an integration over a predetermined number of clock cycles of the difference between one of the forward equalization coefficients and one of the decision feedback equalization coefficients. Alternatively or additionally, the clock generator generates a phase change of the clock signal responsive to at least one integration of the difference between one of the forward equalization coefficients and one of the decision feedback equalization coefficients.
There is further provided, in accordance with a preferred embodiment of the present invention, a receiver of baseband signals from a communications line, including:
an A/D converter, which samples and digitizes the signals to generate digitized data;
an equalization section, including a pipeline which receives the digitized data and generates equalized output data representative of data input to the line, the pipeline including a plurality of multipliers, which multiply data input thereto by respective multiplication coefficients, and a plurality of adders, which receive and sum the multiplied data; and
a decision module, which compares the equalized output data to one or more predetermined thresholds so as to generate decision data indicative of a level of the input data, which decision data are input to the pipeline together with the digitized data.
Preferably, the pipeline includes a plurality of delay registers, intermediate the adders, which transfer the data from one of the adders to the next in the pipeline.
In a preferred embodiment, the decision module generates an error signal responsive to a deviation of the equalized data relative to the decision data, and the multipliers multiply the digitized data and the decision data by respective coefficients generated by the equalization section responsive to the error signal. Preferably, one or more of the coefficients are generated by multiplying the error signal by the digitized data or, alternatively or additionally, by multiplying the error signal by the decision data.
Preferably, each of at least some of the adders in the pipeline receives and sums a respective one of the multiplied digitized data and a corresponding one of the multiplied decision data, wherein at least one of the at least some of the adders receives and sums the respective multiplied digitized data and multiplied decision data together with an output of a preceding one of the adders in the pipeline.
In a preferred embodiment, the pipeline includes a pre-decoding section, which subtracts each of the input data from a preceding one of the data so as to substantially eliminate baseline wander from the signals.
There is additionally provided, in accordance with a preferred embodiment of the present invention, a method for processing baseband signals from a communications line characterized by baseline wander, including:
receiving and sampling the signals and subtracting each sample from a preceding sample, in a pre-decoding section, so as to generate corrected data; and
receiving the corrected data, in an equalization section, and generating equalized output data therefrom representative of data input to the line and generally free of the baseline wander.
Preferably, the method includes digitizing the signals in an A/D converter and transmitting the digitized signals to the pre-decoding section or, alternatively, digitizing the corrected data in an A/D converter and transmitting the digitized corrected data to the equalization section.
Preferably, generating equalized output data includes passing the data through a pipeline, including one or more delay stages and one or more respective adders, and subtracting each sample includes inverting each sample and inputting the inverted sample to the pipeline.
Preferably, receiving the signals includes receiving signals encoded in an ordered level change format, most preferably an MLT-3 format.
Preferably, the method includes comparing the equalized data to one or more predetermined thresholds and responsive thereto outputting decision data corresponding to a level of the input data, wherein comparing the data preferably includes outputting an error signal, indicative of a deviation of the equalized output data relative to the level of the input data, and wherein equalizing the data includes processing the data responsive to the error signal.
In a preferred embodiment, equalizing the data includes generating, responsive to the error signal, one or more forward equalization coefficients, which multiply the corrected data, and one or more decision feedback equalization coefficients, which multiply the decision data, and summing the multiplied corrected data and decision data. Preferably, the method further includes generating a clock signal to time the sampling of the signals, wherein the clock signal is adjusted responsive to one or more of the coefficients.
There is moreover provided, in accordance with a preferred embodiment of the present invention, a method of processing baseband signals received from a communications line, including:
sampling and digitizing the signals to generate digitized data;
determining one or more equalization coefficients responsive to a level of the digitized data;
equalizing the digitized data to generate equalized output data representative of data input to the line by multiplying the digitized data by the one or more equalization coefficients; and
generating a variable clock signal responsive to at least one of the one or more equalization coefficients, which clock signal is used to time the sampling.
Preferably, generating the clock signal includes varying a phase of the clock signal responsive to the decision data, most preferably by providing a plurality of clock signals having different, respective phases, and selecting one of the plurality of signals responsive to the decision data.
Alternatively or additionally, generating the clock signal includes varying a frequency of the clock signal responsive to the decision data.
In a preferred embodiment, determining the one or more coefficients includes generating an error signal indicative of a deviation of the equalized output data relative to the data input to the line and determining one or more of the coefficients responsive to the error signal. Preferably, determining the one or more equalization coefficients includes determining one or more forward equalization coefficients and one or more decision feedback equalization coefficients, and equalizing the data includes multiplying the digitized data by the one or more forward equalization coefficients and multiplying the decision data by the one or more decision feedback equalization coefficients and adding the multiplied data together in a pipeline, and generating the clock signal is performed responsive to one or more of the coefficients. Most preferably, generating the clock signal includes generating a signal responsive to a precursor coefficient of the one or more forward equalization coefficients and a most significant one of the one or more decision feedback equalization coefficients.
In a preferred embodiment, generating the clock signal includes integrating at least one of the coefficients over a predetermined number of clock cycles to generate an integrated output and varying the clock signal responsive to the integrated output. Preferably, varying the clock signal includes determining a primary difference between the integrated output and the at least one of the coefficients and varying the clock signal responsive to the primary difference. Additionally or alternatively, varying the clock signal includes determining a secondary difference corresponding to a variation over time in the primary difference and varying the clock signal responsive to the secondary difference.
In a preferred embodiment, generating the clock signal includes varying the clock signal responsive to a difference between one of the forward equalization coefficients and one of the decision feedback equalization coefficients. Preferably, varying the clock signal includes generating a frequency offset of the clock signal responsive to an integration over a predetermined number of clock cycles of the difference between the one of the forward equalization coefficients and the one of the decision feedback equalization coefficients. Alternatively or additionally, varying the clock signal includes generating a phase change of the clock signal responsive to at least one integration of the difference between the one of the forward equalization coefficients and the one of the decision feedback equalization coefficients.
There is further provided, in accordance with a preferred embodiment of the present invention, a method of processing baseband signals received from a communications line, including:
sampling and digitizing the signals to generate digitized data;
equalizing the digitized data by processing the data in a pipeline to generate equalized output data representative of data input to the communications line, which processing includes:
multiplying data input to the pipeline by a plurality of respective multiplication coefficients; and
summing the multiplied data together in the pipeline;
comparing the equalized output data to one or more predetermined thresholds so as to generate decision data indicative of a level of the input data; and
inputting the decision data to the pipeline together with the digitized data.
Preferably, multiplying and summing the data include multiplying and summing data in a plurality of pipeline stages, and equalizing the data includes delaying the data in the pipeline between one stage and the next.
In a preferred embodiment, comparing the equalized data comprises generating an error signal responsive to a deviation of the equalized data relative to the decision data, and multiplying the digitized data and the decision data includes multiplying the data by coefficients generated responsive to the error signal. Preferably, multiplying the data includes multiplying the data by coefficients generated by multiplying the error signal by the digitized data. Additionally or alternatively, multiplying the data includes multiplying the data by coefficients generated by multiplying the error signal by the decision data.
Preferably, summing the data includes summing a respective one of the multiplied digitized data and a corresponding one of the multiplied decision data at one or more stages in the pipeline. Preferably, summing the data at the one or more stages includes summing the multiplied digitized data and the multiplied decision data together with an output of a preceding stage in the pipeline.
In a preferred embodiment, the method includes substantially eliminating baseline wander from the signals by subtracting each of the data input to the pipeline from a preceding one of the data input to the pipeline.